Simulation and analysis of III-V nMOS transistors
Submitted by Enrico Caruso on Sat, 07/06/2014 - 17:45
Recently, MOSFET technology entered in a phase of power-constrained scenario where the power density cannot increase without incurring in substantial packaging and cooling costs that make these chips impractical for most applications. To prevent the chip from overheating, the supply voltage should be limited while maintaining the ability to deliver high on-currents for each new generation of technology. A solution to reach this target is change the traditional Silicon channel with III-V compound semiconductors because of their extraordinary intrinsic mobility and high injection velocity. My PhD activity is focused on the simulation of nanoscale MOSFETs with III-V semiconductor channel using advanced models for the band structure of the channel material and to determine the current drive of such devices.
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